The invention relates to a method of manufacturing a semiconductor device whereby a field effect transistor is provided at a surface of a semiconductor body, which transistor comprises a source and a drain of a first conductivity type mutually separated by a channel region of a second, opposite conductivity type and comprising a gate electrode which is insulated from the channel region by a first insulating layer, whereby the first insulating layer is provided on the surface of the semiconductor body and is covered with a conductive layer, an etching mask is provided and a gate electrode is etched from the conductive layer under the masking of this mask, exposed portions of the gate electrode are covered with insulating material, the semiconductor body is doped with an impurity on both sides of the gate electrode for the formation of the source and drain, the assembly is covered with a further insulating layer which at the area of at least either the source or the drain is provided with a contact window which lies partly above the gate electrode, and an electrical connection is provided via the contact window.
In such a method, whereby the gate electrode is entirely encapsulated in insulating material, any contact windows to the source and the drain are allowed to lie partly above the gate electrode. When these windows are provided, accordingly, no alignment tolerances relative to the gate electrode need be taken into account, so that a considerable higher packing density can be realized.
A method of the kind mentioned in the opening paragraph is known from a European patent application which was laid open to public inspection under no. 81.999. In the method described therein, the gate electrode is formed from a conductive layer of doped polycrystalline silicon. The exposed portions of the gate electrode are covered with insulating material in that the entire assembly is subjected to an oxidizing atmosphere, so that a layer of silicon oxide is formed on the gate electrode. Adjacent the gate electrode, the semiconductor body is (still) undoped at that moment with the object of growing a substantially thinner silicon oxide layer thereon. After the source and drain have been formed, a further silicon oxide layer is deposited into which contact windows are etched at the areas of the source and drain. Owing to the greater oxide thickness at the area of the gate electrode compared with said thickness at the area of the source and the drain, the contact windows need not be aligned relative to the gate electrode.
The known method, however, has the disadvantage that restrictions are imposed on the choice of material for the contacting layer. This is because the gate electrode must have an oxidizable surface in the known method. In addition, the known method is found to be not well reproducible in practice for field effect transistors of very small dimensions, for example, with a source to drain distance below 2 .mu.m. This latter disadvantage is supposed to be due to an encroachment on the gate dielectric during the thermal oxidation of the gate electrode leading to a so called `bird's beak` under the gate electrode.